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| 1. general description the lpc82x are an arm cortex-m0+ based, low-cost 32-bit mcu family operating at cpu frequencies of up to 30 mhz. the lpc82x support up to 32 kb of flash memory and 8 kb of sram. the peripheral complement of the lpc82x includes a crc engine, four i 2 c-bus interfaces, up to three usarts, up to tw o spi interfaces, one multi-rate timer, self-wake-up timer, and state-configurable timer with pwm function (sctimer/pwm), a dma, one 12-bit adc and one analog comparator, function-configurable i/o ports through a switch matrix, an input pattern match engine, and up to 29 general-purpose i/o pins. for additional documentation related to the lpc82x parts, see section 18 . 2. features and benefits ? system: ? arm cortex-m0+ processor (r evision r0p1), running at frequencies of up to 30 mhz with single-cycle multiplier and fast single-cycle i/o port. ? arm cortex-m0+ built-in nested vectored interrupt controller (nvic). ? system tick timer. ? ahb multilayer matrix. ? serial wire debug (swd) with four break points and two watch points. jtag boundary scan (bsdl) supported. ? mtb ? memory: ? up to 32 kb on-chip flash programming memory with 64 byte page write and erase. code read protection (crp) supported. ? 8 kb sram. ? rom api support: ? boot loader. ? on-chip rom apis for adc, spi, i2c, usart, power configuration (power profiles) and integer divide. ? flash in-application programming (iap) and in-system programming (isp). ? digital peripherals: ? high-speed gpio interface connected to th e arm cortex-m0+ io bus with up to 29 general-purpose i/o (gpio) pins with conf igurable pull-up/pu ll-down resistors, programmable open-drain mode, input inverter, and digital filter. gpio direction control supports independent set/clear/toggle of individual bits. ? high-current source output driver (20 ma) on four pins. lpc82x 32-bit arm cortex-m0+ microcontrolle r; up to 32 kb flash and 8 kb sram; 12-bit adc; comparator rev. 1 ? 1 october 2014 product data sheet
lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 2 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? high-current sink driver (20 ma) on two true open-drain pins. ? gpio interrupt generation capability with boolean pattern-matching feature on eight gpio inputs. ? switch matrix for flexible config uration of each i/o pin function. ? crc engine. ? dma with 18 channels and 9 trigger inputs. ? timers: ? state configurable timer (sctimer/pwm ) with input and output functions (including capture and match) for timing and pwm applications. each sctimer/pwm input is multip lexed to allow selecting fr om several input sources such as pins, adc interrupt, or comparator output. ? four channel multi-rate timer (mrt) for repetitive interrupt generation at up to four programmable, fixed rates. ? self-wake-up timer (wkt) clocked from either the irc, a low-power, low-frequency internal oscilla tor, or an external clock input in the a lways-on power domain. ? windowed watchdog timer (wwdt). ? analog peripherals: ? one 12-bit adc with up to 12 input channel s with multiple inte rnal and external trigger inputs and with sample rates of up to 1.2 msamples/s. the adc supports two independent conversion sequences. ? comparator with four input pins and external or internal reference voltage. ? serial peripherals: ? three usart interfaces with pin function s assigned through the switch matrix and one common fractional baud rate generator. ? two spi controllers with pin functions assigned through the switch matrix. ? four i 2 c-bus interfaces. one i2c supports fast-mode plus with 1 mbit/s data rates on two true open-drain pins and listen mode. three i2cs support data rates up to 400 kbit/s on standard digital pins. ? clock generation: ? 12 mhz internal rc oscillator trimmed to 1. 5 % accuracy that can optionally be used as a system clock. ? crystal oscillator with an operating range of 1 mhz to 25 mhz. ? programmable watchdog osc illator with a frequency range of 9.4 khz to 2.3 mhz. ? pll allows cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. may be run from the system oscilla tor, the external clock input, or the internal rc oscillator. ? clock output function with divider that can reflect all internal clock sources. ? power control: ? power consumption in active mode as low as 90 ua/mhz in low-current mode using the irc as the clock source. ? integrated pmu (power management unit) to minimize power consumption. ? reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. ? wake-up from deep-sleep and power-down modes on activity on usart, spi, and i2c peripherals. ? timer-controlled self wake-up from deep power-down mode. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 3 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? power-on reset (por). ? brownout detect (bod). ? unique device serial number for identification. ? single power supply (1.8 v to 3.6 v). ? operating temperature range -40 c to +105 c. ? available in a tssop20 and hvqfn33 (5x5) package. 3. applications 4. ordering information 4.1 ordering options ? sensor gateways ? simple motor control ? industrial ? portables and wearables ? gaming controllers ? lighting ? 8/16-bit applications ? motor control ? consumer ? fire and security applications ? climate control table 1. ordering information type number package name description version lpc824m201jhi33 hvqfn33 hvqfn: plastic thermal enh anced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc822m101jhi33 hvqfn33 hvqfn: plastic thermal enh anced very thin quad flat package; no leads; 33 terminals; body 5 ? 5 ? 0.85 mm n/a lpc824m201jdh20 tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 lpc822m101jdh20 tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 table 2. ordering options type number flash/ kb sram/ kb usart i 2 c spi adc channels comparator gpio package lpc824m201jhi33 32 8 3 4 2 12 y 29 hvqfn33 lpc822m101jhi33 16 4 3 4 2 12 y 29 hvqfn33 lpc824m201jdh20 32 8 3 4 2 5 y 16 tssop20 lpc822m101jdh20 16 4 3 4 2 5 y 16 tssop20 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 4 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 5. marking the hvqfn33 packages typically have the following top-side marking: 82xj xx xx yywwxr the tssop20 packages typically have the following top-side marking: lpc82x mx01j xxxxxxxx zzywwxr in the last line, field ?y? or ?yy? states the year the device was manufactured. field ?ww? states the week the device was manufactured during that year. field ?r? states the chip revision. fig 1. tssop20 package marking fig 2. hvqfn33 package marking aaa-014766 terminal 1 index area 1 20 aaa-014382 terminal 1 index area lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 5 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 6. block diagram gray-shaded blocks show peripherals that can provide hardware triggers or fi xed dma requests for dma transfers. fig 3. lpc82x block diagram sram 4/8 kb arm cortex-m0+ test/debug interface flash 16/32 kb high-speed gpio ahb to apb bridge clock generation, power control, system functions reset, clkin clocks and controls lpc82xm aaa-014399 slave slave slave rom slave crc slave master pin interrupts/ pattern match ahb-lite bus irc wdosc bod por spi0/1 usart0/1/2 sda scl sct_pin[3:0] 29 x pio0 29 x wwdt iocon pmu self wake-up timer multi-rate timer i 2 c0/1/2/3 sctimer/ pwm switch matrix sct_out[6:0] comparator xtalin xtalout acmp_o syscon rxd, cts txd, rts acmp_i[4:1] vddcmp adc adc_[11:0] sck, ssel miso, mosi always-on power domain xtal sclk clkout swclk, swd input mux dma lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 6 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 7. pinning information 7.1 pinning fig 4. pin configuration tssop20 package tssop20 pio0_23/adc_3/acmp_i4 pio0_14/adc_2/acmp_i3 pio0_17/adc_9 pio0_0/acmp_i1/tdo pio0_13/adc_10 vrefp pio0_12 vrefn reset/pio0_5 v ss pio0_4/adc_11/wakeup/trst v dd swclk/pio0_3/tck pio0_8/xtalin swdio/pio0_2/tms pio0_9/xtalout pio0_11/i2c0_sda pio0_1/acmp_i2/clkin/tdi pio0_10/i2c0_scl pio0_15 aaa-011391 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 fig 5. pin configuration hvqfn33 package aaa-011396 transparent top view pio0_9/xtalout swdio/pio0_2/tms pio0_11/i2c0_sda pio0_8/xtalin swclk/pio0_3/tck v dd pio0_28/wktclkin vrefn pio0_4/adc_11/trst vrefp pio0_5/reset pio0_7/adc_0 pio0_12 pio0_6/adc_1/vddcmp pio0_13/adc_10 pio0_0/acmp_i1/tdo pio0_10/i2c0_scl pio0_16 pio0_27 pio0_26 pio0_25 pio0_24 pio0_15 pio0_1/acmp_i2/clkin/tdi pio0_17/adc_9 pio0_18/adc_8 pio0_19/adc_7 pio0_20/adc_6 pio0_21/adc_5 pio0_22/adc_4 pio0_23/adc_3/acmp_i4 pio0_14/adc_2/acmp_i3 8 17 7 18 6 19 5 20 42 1 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 7 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 7.2 pin description the pin description table ta b l e 3 shows the pin functions that are fixed to specific pins on each package. these fixed-pin functions are se lectable through the switch matrix between gpio and the comparator, adc, swd, reset , and the xtal pins. by default, the gpio function is selected except on pins pio0 _2, pio0_3, and pio0_5. jtag functions are available in boundary scan mode only. movable function for the i2c, usart, spi, and sct pin functions can be assigned through the switch matrix to any pin that is not power or ground in place of the pin?s fixed functions. the following exceptions apply: do not assign more than one output to any pin. however, more than one input can be assigned to a pin. once any function is assign ed to a pin, the pin?s gpio functionality is disabled. pin pio0_4 triggers a wake-up from deep power-down mode. if the part must wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. the jtag functions tdo, tdi, tck, tms, and trst are selected on pins pio0_0 to pio0_4 by hardware when the part is in boundary scan mode. table 3. pin description symbol tssop20 hvqfn33 reset state [1] type description pio0_0/acmp_i1/ tdo 19 24 [2] i; pu io pio0_0 ? general-purpose port 0 input/output 0. in isp mode, this is the u0_rxd pin. in boundary scan mode: tdo (test data out). a acmp_i1 ? analog comparator input 1. pio0_1/acmp_i2/ clkin/tdi 12 16 [2] i; pu io pio0_1 ? general-purpose port 0 input/output 1. in boundary scan mode: tdi (test data in). a acmp_i2 ? analog comparator input 2. i clkin ? external clock input. swdio/pio0_2/ tms 87 [4] i; pu io swdio ? serial wire debug i/o. swdio is enabled by default on this pin. in boundary scan mode: tms (test mode select). i/o pio0_2 ? general-purpose port 0 input/output 2. swclk/pio0_3/ tck 76 [4] i; pu i swclk ? serial wire clock. swclk is enabled by default on this pin. in boundary scan mode: tck (test clock). io pio0_3 ? general-purpose port 0 input/output 3. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 8 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller pio0_4/adc_11/ trstn/wakeup 64 [3] i; pu io pio0_4 ? general-purpose port 0 input/output 4. in boundary scan mode: trst (test reset). in isp mode, this pin is the u0_txd pin. this pin triggers a wake-up from deep power-down mode. if the part must wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. this pin should be pulled high externally before entering deep power-down mode. a low-going puls e as short as 50 ns causes the chip to exit deep power-down mode and wakes up the part. a adc_11 ? adc input 11. reset /pio0_5 5 3 [7] i; pu io reset ? external reset input: a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. in deep power-down mode, this pin must be pulled high externally. the reset pin can be left unconnected or be used as a gpio or for any movable function if an external reset function is not needed and the deep power-down mode is not used. i pio0_5 ? general-purpose port 0 input/output 5. pio0_6/adc_1/ vddcmp -23 [10] i; pu io pio0_6 ? general-purpose port 0 input/output 6. a adc_1 ? adc input 1. a vddcmp ? alternate reference voltage for the analog comparator. pio0_7/adc_0 - 22 [2] i; pu io pio0_7 ? general-purpose port 0 input/output 7. a adc_0 ? adc input 0. pio0_8/xtalin 14 18 [8] i; pu io pio0_8 ? general-purpose port 0 input/output 8. a xtalin ? input to the oscillator circuit and internal clock generator circuits. input volt age must not exceed 1.95 v. pio0_9/xtalout 13 17 [8] i; pu io pio0_9 ? general-purpose port 0 input/output 9. a xtalout ? output from the oscillator circuit. pio0_10/i2c0_scl 10 9 [6] inactive i; f pio0_10 ? general-purpose port 0 input/output 10 (open-drain). i2c0_scl ? open-drain i 2 c-bus clock input/output. high-current sink if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_11/i2c0_sda 9 8 [6] inactive i; f pio0_11 ? general-purpose port 0 inpu t/output 11 (open-drain). i2c0_sda ? open-drain i 2 c-bus data input/output. high-current sink if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_12 4 2 [4] i; pu io pio0_12 ? general-purpose port 0 in put/output 12. isp entry pin. a low level on this pin during reset starts the isp command handler. pio0_13/adc_10 3 1 [2] i; pu io pio0_13 ? general-purpose port 0 input/output 13. a adc_10 ? adc input 10. table 3. pin description symbol tssop20 hvqfn33 reset state [1] type description lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 9 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [1] pin state at reset for default function: i = input; ai = anal og input; o = output; pu = internal pull-up enabled (pins pulle d up to full v dd level); ia = inactive, no pull-up/down enabled; f = floati ng. for pin states in the different power modes, see section 14.5 ? pin states in different power modes ? . for termination on unused pins, see section 14.4 ? termination of unused pins ? . [2] 5 v tolerant pin providing standard digita l i/o functions with configurable modes, configurable hysteresis, and analog input . when configured as an analog input, the digital section of t he pin is disabled, and the pin is not 5 v tolerant. pio0_14/ acmp_i3/adc_2 20 25 [2] i; pu io pio0_14 ? general-purpose port 0 input/output 14. a acmp_i3 ? analog comparator common input 3. a adc_2 ? adc input 2. pio0_15 11 15 [5] i; pu io pio0_15 ? general-purpose port 0 input/output 15. pio0_16 - 10 [4] i; pu io pio0_16 ? general-purpose port 0 input/output 16. pio0_17/adc_9 2 32 [2] i; pu io pio0_17 ? general-purpose port 0 input/output 17. a adc_9 ? adc input 9. pio0_18/adc_8 - 31 [2] i; pu io pio0_18 ? general-purpose port 0 input/output 18. a adc_8 ? adc input 8. pio0_19/adc_7 - 30 [2] i; pu io pio0_19 ? general-purpose port 0 input/output 19. a adc_7 ? adc input 7. pio0_20/adc_6 - 29 [2] i; pu io pio0_20 ? general-purpose port 0 input/output 20. a adc_6 ? adc input 6. pio0_21/adc_5 - 28 [2] i; pu io pio0_21 ? general-purpose port 0 input/output 21. a adc_5 ? adc input 5. pio0_22/adc_4 - 27 [2] i; pu io pio0_22 ? general-purpose port 0 input/output 22. a adc_4 ? adc input 4. pio0_23/adc_3/ acmp_i4 126 [2] i; pu io pio0_23 ? general-purpose port 0 input/output 23. a adc_3 ? adc input 3. a acmp_i4 ? analog comparator common input 4. pio0_24 - 14 [5] i; pu io pio0_24 ? general-purpose port 0 input/output 24. pio0_25 - 13 [5] i; pu io pio0_25 ? general-purpose port 0 input/output 25. pio0_26 - 12 [5] i; pu io pio0_26 ? general-purpose port 0 input/output 26. pio0_27 - 11 [5] i; pu io pio0_27 ? general-purpose port 0 input/output 27. pio0_28/ wktclkin -5 [3] i; pu io pio0_28 ? general-purpose port 0 input/output 28. this pin can host an external clock for the self-wake-up timer. to use the pin as a self-wake-up timer clock input, select the external clock in the wake-up timer ctrl register. the external clock input is active in all power modes, including deep power-down. v dd 15 19 - - supply voltage for the i/o pad ring, the core voltage regulator, and the analog peripherals. vss 16 33 - - ground. vrefn 17 20 - - adc negative reference voltage. vrefp 18 21 - - adc positive reference voltage. must be equal or lower than v dd . table 3. pin description symbol tssop20 hvqfn33 reset state [1] type description lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 10 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. this pin is active in deep power-down mode and includes a 20 ns glitch filter (active in all power modes). in deep power-down mode, pulling the wakeup pin low wakes up the chip. the wake-up pin function can be di sabled and the pin can be used for other purposes, if the w kt low-power oscillator is enabl ed for waking up the part from deep power-down mode. see table 16 ? dynamic characteristics: wktclkin pin ? for the wktclkin input. [4] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis; includes high-current output driver. [5] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis. [6] true open-drain pin. i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. do not use this pad for high-speed appl ications such as spi or usart. the pi n requires an external pull-up to provide out put functionality. when power is switched off, this pin is floating and does not disturb the i2c lines. open-drain configuration ap plies to all functions on this pin. [7] see figure 10 for the reset pad configuration. this pin includes a 20 ns glitch filter (active in all power modes). reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an external pull-up resistor is required on this pin for the deep power-down mode. [8] 5 v tolerant pin providing standard digital i/o functions wi th configurable modes, configur able hysteresis, and analog i/o f or the system oscillator. when configured for xtalin and xtalout, the digital se ction of the pin is disabled, and the pin is not 5 v tolerant . [9] the wktclkin function is enabled in the dpdctrl re gister in the pmu. see the lpc82x user manual. [10] the digital part of this pin is 3 v tolerant pin due to s pecial analog functionality. pin pr ovides standard digital i/o fun ctions with configurable modes, confi gurable hysteresis, and an analog input. when configur ed as an analog input, the digital section of th e pin is disabled. table 4. movable functions (assi gn to pins pio0_0 to pio0_28 through switch matrix) function name type description u0_txd o transmitter output for usart0. u0_rxd i receiver input for usart0. u0_rts o request to send output for usart0. u0_cts i clear to send input for usart0. u0_sclk i/o serial clock input/output for usart0 in synchronous mode. u1_txd o transmitter output for usart1. u1_rxd i receiver input for usart1. u1_rts o request to send output for usart1. u1_cts i clear to send input for usart1. u1_sclk i/o serial clock input/output for usart1 in synchronous mode. u2_txd o transmitter output for usart2. u2_rxd i receiver input for usart2. u2_rts o request to send output for usart1. u2_cts i clear to send input for usart1. u2_sclk i/o serial clock input/output for usart1 in synchronous mode. spi0_sck i/o serial clock for spi0. spi0_mosi i/o master out slave in for spi0. spi0_miso i/o master in slave out for spi0. spi0_ssel0 i/o slave select 0 for spi0. spi0_ssel1 i/o slave select 0 for spi1. spi0_ssel2 i/o slave select 0 for spi2. spi0_ssel3 i/o slave select 0 for spi3. spi1_sck i/o serial clock for spi1. spi1_mosi i/o master out slave in for spi1. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 11 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller spi1_miso i/o master in slave out for spi1. spi1_ssel0 i/o slave select 0 for spi1. spi1_ssel1 i/o slave select 1 for spi1. sct_pin0 i pin input 0 to the sct input multiplexer. sct_pin1 i pin input 1 to the sct input multiplexer. sct_pin2 i pin input 2 to the sct input multiplexer. sct_pin3 i pin input 3 to the sct input multiplexer. sct_out0 o sct output 0. sct_out1 o sct output 1. sct_out2 o sct output 2. sct_out3 o sct output 3. sct_out4 o sct output 4. sct_out5 o sct output 5. i2c1_sda i/o i 2 c1-bus data input/output. i2c1_scl i/o i 2 c1-bus clock input/output. i2c2_sda i/o i 2 c2-bus data input/output. i2c2_scl i/o i 2 c2-bus clock input/output. i2c3_sda i/o i 2 c3-bus data input/output. i2c3_scl i/o i 2 c3-bus clock input/output. adc_pintrig0 i adc external pin trigger input 0. adc_pintrig1 i adc external pin trigger input 1. acmp_o o analog comparator output. clkout o clock output. gpio_int_bmat o output of the pattern match engine. table 4. movable functions (assi gn to pins pio0_0 to pio0_28 through switch matrix) function name type description lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 12 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 8. functional description 8.1 arm cortex-m0+ core the arm cortex-m0+ core runs at an operating frequency of up to 30 mhz using a two-stage pipeline. the core revision is r0p1. integrated in the core are th e nvic and serial wire debug with four breakpoints and two watchpoints. the arm cortex-m0+ core supports a single-cycle i/o enabled port for fast gpio access. the core includes a single-cycle multiplier and a system tick timer. 8.2 on-chip flash program memory the lpc82x contain up to 32 kb of on-c hip flash program memory. the flash memory supports a 64 byte page size with page write and erase. 8.3 on-chip sram the lpc82x contain a total of 8 kb on-chip static ram data memory in two separate sram blocks with one combined clock for both sram blocks. 8.4 on-chip rom the on-chip rom contains the bootloader and the following app lication programming interfaces (apis): ? in-system programming (isp) and in-application programming (iap) support for flash including iap erase page command. ? power profiles for configuring po wer consumption and pll settings ? 32-bit integer division routines ? apis to use the following peripherals: ? spi ? usart ? i2c ? adc 8.5 memory map the lpc82x incorporates seve ral distinct memory regions. figure 6 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the arm private peripheral bu s includes the arm core registers for controlling the nvic, the system tick timer (systick), and the reduced power modes. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 13 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 8.6 nested vectored inte rrupt controller (nvic) the nested vectored interrupt controller (nvi c) is part of the cortex-m0+. the tight coupling to the cpu allows for lo w interrupt latency and efficient processing of late arriving interrupts. 8.6.1 features ? nested vectored interrupt controller is a part of the arm cortex-m0+. fig 6. lpc82x memory mapping apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4005 0000 0x4005 8000 0x4005 c000 0x4006 0000 0x4006 4000 0x4006 8000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 mrt reserved reserved 12-bit adc self wake-up timer reserved wwdt analog comparator pmu 30 - 31 reserved 0 1 2 3 4 5 6 7 8 9 0x4002 c000 0x4003 0000 0x4003 4000 dma trigmux 10 input mux 11 reserved 12 reserved 13 16 15 14 17 18 reserved reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1fff 0000 0x1fff 3000 0x2000 0000 0x5000 0000 0x5000 4000 0xffff ffff reserved reserved reserved 0x4000 0000 0x4008 0000 apb peripherals crc 0x5000 8000 sctimer/pwm 0x5000 c000 0xa000 0000 gpio 0xa000 4000 0xa000 8000 gpio pint 0x1000 1000 4 kb sram0 0x1001 2000 4 kb sram1 0x1000 0000 lpc82x 0x0000 8000 32 kb on-chip flash 12 kb boot rom 0x1400 0000 0x1400 1000 4 kb mtb registers 0x0000 0000 0x0000 00c0 active interrupt vectors reserved reserved dma reserved flash controller spi0 reserved switch matrix iocon system control (syscon) 19 reserved 0x4005 4000 20 i2c0 21 i2c1 22 23 spi1 24 reserved 0x4006 c000 0x4007 0000 usart0 25 26 usart1 27 usart2 0x4007 4000 28 i2c2 0x4007 8000 29 i2c3 reserved 0xe000 0000 0xe010 0000 private peripheral bus aaa-015072 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 14 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? tightly coupled interrupt controller provides low interrupt latency. ? controls system exceptions and peripheral interrupts. ? supports 32 vectored interrupts. ? in the lpc82x, the nvic supports vectored interrupts for each of the peripherals and the eight pin interrupts. ? four programmable interrupt priority levels with hardware prio rity level masking. ? software interrupt generation using the arm exceptions svcall and pendsv. ? supports nmi. 8.6.2 interrupt sources each peripheral device has at least one interr upt line connected to the nvic but can have several interrupt flags. individual interrupt flags can also represent more than one interrupt source. 8.7 system tick timer the arm cortex-m0+ includes a 24-bit system tick timer (systick) that is intended to generate a dedicated systick exception at a fixed time interval (typically 10 ms). 8.8 i/o configuration the iocon block controls the configuration of the i/o pins. each digital or mixed digital/analog pin with the pio0_n designato r (except the true open-drain pins pio0_10 and pio0_11) in ta b l e 3 can be configured as follows: ? enable or disable the weak internal pull-up and pull-down resistors. ? select a pseudo open-drain mode. the input cannot be pulled up above v dd . the pins are not 5 v tolerant when v dd is grounded. ? program the input glitch filter with differ ent filter constants using one of the iocon divided clock signals (ioconclkcdiv, see figure 9 ? lpc82x clock generation ? ). you can also bypass the glitch filter. ? invert the input signal. ? hysteresis can be en abled or disabled. ? for pins pio0_10 and pio0_11, select the i2c-mode and output driver for standard digital operation, for i2c standard and fast modes, or for i2c fast mode+. ? the switch matrix setting enables the analog input mode on pins with analog and digital functions. enabling the analog mo de disconnects the digital functionality. remark: the functionality of each i/o pin is flexib le and is determined entirely through the switch matrix. see section 8.9 for details. 8.8.1 standard i/o pad configuration figure 7 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver with conf igurable open-drain output. ? digital input: weak pull-up resistor (pmos device) enabled/disabled. ? digital input: weak pull-down resistor (nmos device) enabled/disabled. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 15 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? digital input: repeater mode enabled/disabled. ? digital input: programmable input digital filter selectable on all pins. ? analog input: selected through the switch matrix. 8.9 switch matrix (swm) the switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowin g to connect many functions like the usart, spi, sct, and i2c functions to any pin that is not power or ground. these functions are called movable functions and are listed in table 4 . functions that need sp ecialized pads like the oscillato r pins xtalin and xtalout can be enabled or disabled through the switch matrix. these functions are called fixed-pin functions and cannot move to other pins. the fixed-pin functions are listed in ta b l e 3 . if a fixed-pin function is disabled, any other mov able function can be assigned to this pin. fig 7. standard i/o pad configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input analog input swm pinenable for analog input pin configured as digital output driver pin configured as digital input pin configured as analog input programmable digital filter aaa-014392 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 16 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 8.10 fast general-purpo se parallel i/o (gpio) device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc82x use accelerated gpio functions: ? gpio registers are on the arm cortex-m0+ io bus for fastest possible single-cycle i/o timing, allowing gpio toggling with rates of up to 15 mhz. ? an entire port value can be written in one instruction. ? mask, set, and clear operations are supported for the entire port. all gpio port pins are fixed-pi n functions that are enabled or disabled on the pins by the switch matrix. therefore each gpio port pin is assigned to one specific pin and cannot be moved to another pin. except for pi ns swdio/pio0_2, swclk/pio0_3, and reset /pio0_5, the switch matrix enables the gpio port pin function by default. 8.10.1 features ? bit level port registers allow a single instruction to set and clear any number of bits in one write operation. ? direction control of individual bits. ? all i/o default to gpio inputs with internal pull-up resistors enabled after reset - except for the i 2 c-bus true open-drain pins pio0_10 and pio0_11. ? pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the iocon block for each gpio pin (see figure 7 ). ? direction (input/output) can be set and cleared individually. ? pin direction bits can be toggled. 8.11 pin interrupt/pattern match engine the pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the nvic. the pattern match engine can be used, with software, to create complex state machines based on pin inputs. any digital pin, independently of the function selected through the switch matrix, can be configured through the syscon block as input to the pi n interrupt or pattern match engine. the registers that control the pin interrupt or pattern match engine are on the io+ bus for fast single-cycle access. 8.11.1 features ? pin interrupts ? up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. each request creates a separate interrupt in the nvic. ? edge-sensitive interrupt pins can interrupt on rising or falling edges or both. ? level-sensitive interrupt pins can be high- or low-active. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 17 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? pin interrupts can wake up the lpc82x from sleep mode, deep-sleep mode, and power-down mode. ? pin interrupt pattern match engine ? up to eight pins can be selected from all digital pins to contribute to a boolean expression. the boolean expression consists of specified levels and/or transitions on various combinations of these pins. ? each minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt request. ? any occurrence of a pattern match can be also programmed to generate an rxev notification to the arm cpu. the rxev signal can be connected to a pin. ? the pattern match engine d oes not facilitate wake-up. 8.12 dma controller the dma controller can access all memori es and the usart, spi, i2c, and adc peripherals using dma requests or triggers. dma transfers can also be triggered by internal events like the adc interrupts, the pin interrupts (pinin t0 and pinint1), the sctimer dma requests, and the dma trigger outputs. 8.12.1 features ? 18 channels with each channel connec ted to peripheral request inputs. ? dma operations can be triggered by on-chip events or by two pin interrupts. each dma channel can select one trigger input from 9 sources. ? priority is user selectable for each channel. ? continuous priority arbitration. ? address cache with two entries. ? efficient use of data bus. ? supports single transfers up to 1,024 words. ? address increment options allow packing and/or unpacking data. 8.12.2 dma trigger input mux (trigmux) each dma trigger is connected to a programma ble multiplexer which connects the trigger input to one of multiple trig ger sources. each multiplexe r supports the same trigger sources: the adc sequence interrupts, the sct dma request lines, and pin interrupts pinint0 and pinint1, and the outputs of th e dma triggers 0 and 1 for chaining dma triggers. 8.13 usart0/1/2 all usart functions are movable functions a nd are assigned to pins through the switch matrix. 8.13.1 features ? maximum bit rates of 1.875 mbit/s in asynchronous mode and 10 mbit/s in synchronous mode for usart functions conn ected to all digital pins except the open-drain pins. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 18 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? 7, 8, or 9 data bits and 1 or 2 stop bits ? synchronous mode with master or slave operation. includes data phase selection and continuous clock option. ? multiprocessor/multidrop (9-bit) mode with software address compare. (rs-485 possible with software address detection and transceiver direction control.) ? parity generation and checking: odd, even, or none. ? one transmit and one receive data buffer. ? rts/cts for hardware signaling for automatic flow control. software flow control can be performed using delta cts detect, transmit disable control, and any gpio as an rts output. ? received data and status can optionally be read from a single register ? break generation and detection. ? receive data is 2 of 3 sample "voting". status flag set when one sample differs. ? built-in baud rate generator. ? a fractional rate divider is shared among all uarts. ? interrupts available for receiver ready, tr ansmitter ready, receiver idle, change in receiver break detect, framing error, pari ty error, overrun, underrun, delta cts detect, and receiver sa mple noise detected. ? separate data and flow control loopback modes for testing. ? baud rate clock can also be output in asynchronous mode. ? supported by on-chip rom api. 8.14 spi0/1 all spi functions are movable functions and are assigned to pins through the switch matrix. 8.14.1 features ? maximum data rates of up to 30 mbit/s in master mode and up to 18 mbit/s in slave mode for spi functions connected to all digital pins except the open-drain pins. ? data frames of 1 to 16 bits supported directly. larger frames supported by software. ? master and slave operation. ? data can be transmitted to a slave without the need to read incoming data, which can be useful while setting up an spi memory. ? control information can optionally be writ ten along with data, which allows very versatile operation, including ?any length? frames. ? one slave select input/output with selectable polarity and flexible usage. remark: texas instruments ssi and national microwire modes are not supported. 8.15 i2c-bus interface (i2c0/1/2/3) the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 19 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller capability to both receive and send information (such as me mory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master. the i2c0-bus functions are fixed-pin function s. all other i2c-bus functions for i2c1/2/3 are movable functions and can be assigned through the switch matrix to any pin. however, only the true open-drain pins provi de the electrical characteristics to support the full i2c-bus specification (see ref. 3 ). 8.15.1 features ? i2c0 supports fast-mode plus with data rates of up to 1 mbit/s in addition to standard and fast modes on two true open-drain pins. ? true open-drain pins provide fail-safe operation: when the power to an i 2 c-bus device is switched off, the sda and scl pins connected to the i 2 c0-bus are floating and do not disturb the bus. ? i2c1/2/3 support standard and fast mode with data rates of up to 400 kbit/s. ? independent master, slave, and monitor functions. ? supports both multi-master and multi-master with slave functions. ? multiple i 2 c slave addresses supported in hardware. ? one slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple i 2 c bus addresses. ? 10-bit addressing supported with software assist. ? supports smbus. 8.16 sctimer/pwm the state configurable timer can perform basic 16-bit and 32-bit timer/counter functions with match outputs and external and inte rnal capture inputs. in addition, the sctimer/pwm can employ up to eight different programmable states, which can change under the control of events, to provide complex timing patterns. the inputs to the sct are multiplexed betwe en movable functions from the switch matrix and internal connections such as the adc threshold compare interrupt, the comparator output, and the arm core signals arm_t xev and debug_halted. the signal on each sct input is selected through the input mux. all outputs of the sct are movable functions and are assigned to pins through the switch matrix. one sct output can also be selected as one of the adc conversion triggers. 8.16.1 features ? each sctimer/pwm supports: ? eight match/capture registers. ? eight events. ? eight states. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 20 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? four inputs. each input is configurable through an input multiplexer to use one of four external pins (connected through the switch matrix) or one of four internal sources. the maximum input signal frequency is 25 mhz. ? six outputs. connected to pins through the switch matrix. ? counter/timer features: ? each sctimer is configurable as two 16-bit counters or one 32-bit counter. ? counters can be clocked by the system clock or selected input. ? configurable as up counters or up-down counters. ? configurable number of match and capture registers. up to eight match and capture registers total. ? upon match create the following events: inte rrupt; stop, limit, halt the timer or change counting direction; toggle outputs. ? counter value can be loaded into capture register triggered by a match or input/output toggle. ? pwm features: ? counters can be used with match regist ers to toggle outputs and create time-proportioned pwm signals. ? up to six single-edge or dual-edge pwm outputs with independent duty cycle and common pwm cycle length. ? event creation features: ? the following conditions define an event: a counter match condition, an input (or output) condition such as a rising or fallin g edge or level, a combination of match and/or input/output condition. ? selected events can limit, halt, start, or stop a counter or change its direction. ? events trigger state changes, output togg les, interrupts, and dma transactions. ? match register 0 can be used as an automatic limit. ? in bidirectional mode, events can be enabled based on the count direction. ? match events can be held until another qualifying event occurs. ? state control features: ? a state is defined by events that can happen in the state while the counter is running. ? a state changes into another state as a result of an event. ? each event can be assigned to one or more states. ? state variable allows sequencing across multiple counter cycles. ? one sctimer match output can be select ed as adc hardware trigger input. 8.16.2 sctimer/pwm input mux (input mux) each input of the sctimer/pwm is connect ed to a programmable multiplexer which allows to connect one of multiple internal or external sources to the input. the available sources are the same for each sctimer/pwm input and can be selected from four pins configured through the switch matrix, t he adc threshold compare interrupt, the comparator output, and the arm core signals ar m_txev and debug_halted. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 21 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 8.17 multi-rate timer (mrt) the multi-rate timer (mrt) provides a repetiti ve interrupt timer with four channels. each channel can be programmed with an independent time interval, and each channel operates independently fr om the other channels. 8.17.1 features ? 31-bit interrupt timer ? four channels independently counting down from individually set values ? bus stall, repeat and one-shot interrupt modes 8.18 windowed watc hdog timer (wwdt) the watchdog timer resets the controller if so ftware fails to service the watchdog timer periodically within a programmable time window. 8.18.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) is generated by the dedicated watchdog oscillator (wdosc). 8.19 self-wake-up timer (wkt) the self-wake-up timer is a 32-bit, loadable down counter. writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. when the counter is used as a wake-up timer, this write can occur prior to entering a reduced power mode. 8.19.1 features ? 32-bit loadable down counter. counter starts automatically when a count value is loaded. time-out generates an interrupt/wake up request. ? the wkt resides in a separate, always-on power domain. ? the wkt supports three clock sources: an external clock on the wktclkin pin, the low-power oscillator, and the irc. the low-pow er oscillator is loca ted in the always-on power domain, so it can be used as the clock source in deep power-down mode. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 22 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? the wkt can be used for waking up the part from any reduced power mode, including deep power-down mode, or for general-purpose timing. 8.20 analog comparator (acmp) the analog comparator with selectable hysteres is can compare voltage levels on external pins and internal voltages. after power-up and after switching the input chan nels of the comparator , the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. settling times are given in ta b l e 2 4 . the analog comparator output is a movable fu nction and is assigned to a pin through the switch matrix. the comparator inputs and the voltage reference are enabled through the switch matrix. 8.20.1 features ? selectable 0 mv, 10 mv ( ? 5 mv), and 20 mv ( ? 10 mv), 40 mv ( ? 20 mv) input hysteresis. ? two selectable external voltages (v dd or vddcmp on pin pio0_6); fully configurable on either positive or negative input channel. ? internal voltage reference from band gap selectable on either positive or negative input channel. ? 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. fig 8. comparator block diagram 4 32 4 acmp_i[4:1] v dd vddcmp adc_0 internal voltage reference edge detect sync comparator level acmp_o, adc trigger comparator edge nvic comparator analog block comparator digital block aaa-012135 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 23 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? voltage ladder source voltage is selectable from an external pin or the main 3.3 v supply voltage rail. ? voltage ladder can be separa tely powered down for applic ations only requiring the comparator function. ? interrupt outp ut is connected to nvic. ? comparator level output is c onnected to output pin acmp_o. ? one comparator output is internally colle cted to the adc trigger input multiplexer. 8.21 analog-to-digital converter (adc) the adc supports a resolution of 12 bit and fast conversion rates of up to 1.2 msamples/s. sequences of analog-to-digita l conversions can be tr iggered by multiple sources. possible trigger so urces are the pin triggers, the sct output sct_out3, the analog comparator output, and the arm txev. the adc includes a hardware threshold compar e function with zero-crossing detection. remark: for best performance, select vrefp and vrefn at the same voltage levels as v dd and v ss . when selecting vrefp and vrefn different from vdd and vss, ensure that the voltage midpoints are the same: (vrefp-vrefn)/2 + vrefn = v dd /2 8.21.1 features ? 12-bit successive approximation analog to digital converter. ? 12-bit conversion rate of up to 1.2 msamples/s. ? two configurable conversion sequ ences with independent triggers. ? optional automatic high/low threshold comparison and zero-crossing detection. ? power-down mode and low-power operating mode. ? measurement range vrefn to vrefp (not to exceed v dd voltage level). ? burst conversion mode for single or multiple inputs. ? hardware calibration mode. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 24 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 8.22 clocking and power control 8.22.1 crystal and internal oscillators the lpc82x include four independent oscillators: 1. the crystal oscillator (syso sc) operating at frequencie s between 1 mhz and 25 mhz. 2. the internal rc oscillator (irc) with a fixed frequency of 12 mhz. 3. the internal low-power, low-frequency oscillator with a nominal frequency of 10 khz with 40% accuracy for use with the self-wake-up timer. 4. the dedicated watchdog oscillator (w dosc) with a programmable nominal frequency between 9.4 khz and 2.3 mhz with 40% accuracy. fig 9. lpc82x clock generation system pll watchdog oscillator irc oscillator irc oscillator watchdog oscillator system oscillator mainclksel (main clock select) syspllclksel system pll clock select clock divider sysahbclkdiv ahb clock 0 (core, system; always-on) clock divider uartclkdiv usart0 usart1 usart2 wwdt irc oscillator wkt low-power oscillator wkt watchdog oscillator irc oscillator system oscillator clock divider clkoutdiv clkout pin clkoutsel (clkout clock select) main clock system clock sysahbclkctrl[1:29] (system clock enable) memories and peripherals, peripheral clocks 29 aaa-012136 ioconclkdiv clock divider iocon glitch filter 7 xtalin clkin xtalout syscon pmu fractional rate generator lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 25 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller each oscillator, except th e low-frequency oscillator, c an be used for more than one purpose as required in a particular application. following reset, the lpc82x operates from the irc until switched by software allowing the part to run without any external crystal and the bootloader code to operate at a known frequency. see figure 9 for an overview of the lpc82x clock generation. 8.22.1.1 internal rc oscillator (irc) the irc may be used as the clock source for the wwdt, and/or as the clock that drives the pll and then the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1.5 % accuracy over the entire voltage and temperature range. the irc can be used as a clock source fo r the cpu with or without using the pll. the irc frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. upon power-up or any chip reset, the lpc82x use the irc as the clock source. software may later switch to one of the other available clock sources. 8.22.1.2 crystal oscillator (sysosc) the crystal oscillator can be used as the clo ck source for the cpu, with or without using the pll. the sysosc operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. 8.22.1.3 internal low-power oscillator and watchdog oscillator (wdosc) the nominal frequency of the wdosc is prog rammable between 9.4 khz and 2.3 mhz. the frequency spread over silicon process variations is ? 40%. the wdosc is a dedicated oscillator for the windowed wwdt. the internal low-power 10 khz ( ? 40% accuracy) oscillator serves as the clock input to the wkt. this oscillator can be configur ed to run in all low-power modes. 8.22.2 clock input an external clock source can be supplied on the selected clkin pin directly to the pll input. when selecting a clock signal for the clki n pin, follow the specifications for digital i/o pins in table 8 ? static characteristics, supply pins ? and table 15 ? dynamic characteristics: i/o pins [1] ? . an 1.8 v external clock source can be su pplied on the xtalin pins to the system oscillator limiting the voltag e of this signal (see section 14.1 ). the maximum frequency for both clock signals is 25 mhz. 8.22.3 system pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 26 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller its frequency range while the pll is provid ing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insu red that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is nominally 100 ? s. 8.22.4 clock output the lpc82x features a clock output function that routes the irc, the sysosc, the watchdog oscillator, or the main clock to t he clkout function. the clkout function can be connected to any digital pin through the switch matrix. 8.22.5 wake-up process the lpc82x begin operation at power-up by using the irc as the clock source allowing chip operation to resume quickl y. if the sysosc, the external clock source, or the pll are needed by the application, software must en able these features and wait for them to stabilize before they are used as a clock source. 8.22.6 power control the lpc82x supports the arm cortex-m0 sleep mode. the cpu clock rate may also be controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals have their ow n clock divider which provides even better power control. 8.22.6.1 power profiles the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile api. the api is accessible through the on-chip rom. the power configuration routine configures the lpc82x for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability. ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. 8.22.6.2 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 27 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.22.6.3 deep-sleep mode in deep-sleep mode, the lpc82x core is in sleep mode and all peripheral clocks and all clock sources are off except fo r the irc and watchdog oscillato r or low-power oscillator if selected. the irc output is disabled. in addit ion, all analog blocks are shut down and the flash is in standby mode. in deep-sleep mode, the application can keep the watchdog oscillator and the bod circuit running for self-timed wake-up and bod protection. the lpc82x can wake up from deep-sleep mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the usart (if the usart is configured in synchronous slave mode), the spi, or the i2c blocks (in slave mode). any interrupt used for waking up from deep-sleep mode must be enabled in one of the syscon wake-up enable r egisters and the nvic. deep-sleep mode saves power and allows for short wake-up times. 8.22.6.4 power-down mode in power-down mode, the lpc82x is in sleep mode and all peripheral clocks and all clock sources are off except for wa tchdog oscillator or low-power oscillator if selected. in addition, all analog blocks and the flash are shut down. in power-down mode, the application can keep the watc hdog oscillator and the bod circ uit running for self-timed wake-up and bod protection. the lpc82x can wake up from power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, or an interrupt from the usart (if the usart is configured in synchronous slave mode), the spi, or the i2c blocks (in slave mode). any interrupt used for waking up from power-down mode must be enabled in one of the syscon wake-up enable r egisters and the nvic. power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 8.22.6.5 deep power-down mode in deep power-down mode, power is shut off to the entire chip except for the wakeup pin and the self-wake-up timer if enabled. four general-purpose registers are available to store information during deep power-down mo de. the lpc82x can wake up from deep power-down mode via the wakeup pin, or without an external signal by using the time-out of the self-wake-up timer (see section 8.19 ). the lpc82x can be prevented from entering deep power-down mode by setting a lock bit in the pmu block. locking out deep power-down mode enables the application to keep the watchdog timer or the bod running at all times. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 28 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. pull the reset pin high to prevent it from floating while in deep power-down mode. 8.23 system control 8.23.1 reset reset has four sources on the lpc82x: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts the irc an d initializes the flash controller. a low-going pulse as short as 50 ns resets the part. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. in deep power-down mode, an external pull-up resistor is required on the reset pin. 8.23.2 brownout detection the lpc82x includes up to four levels for monitoring the voltage on the v dd pin. if this voltage falls below one of the selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic to cause a cpu interrupt. alternatively, so ftware can monitor the signal by reading a dedicated status register. four threshold levels can be selected to cause a forced reset of the chip. fig 10. reset pad configuration 9 6 6 u h v h w d d d 9 ' ' 9 ' ' 9 ' ' 5 s x ( 6 ' ( 6 ' q v 5 & * / , 7 & + ) , / 7 ( 5 3 , 1 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 29 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 8.23.3 code security (code read protection - crp) crp provides different levels of security in th e system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. programming a specific pattern in to a dedicated flash location invokes crp. iap commands are not affected by the crp. in addition, isp entry via the isp entry pi n can be disabled without enabling crp. for details, see the lpc82x user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors cannot be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 selected , fully disables any access to the chip via the swd pins and the isp. this mode ef fectively disables isp override using the isp entry pin as well. if necessary, the application must provide a flash update mechanism using iap calls or using a call to the reinvoke isp command to enable flash update via the usart. in addition to the three crp levels, sampling of the isp entry pin for valid user code can be disabled. for details, see the lpc82x user manual . 8.23.4 apb interface the apb peripherals are located on one apb bus. 8.23.5 ahblite the ahblite connects the cpu bus of the ar m cortex-m0+ to the flash memory, the main static ram, the crc, the dma, the rom, and the apb peripherals. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 30 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 8.24 emulation and debugging debug functions are integrated into the arm cortex-m0+. serial wire debug functions are supported in addition to a standard jtag boundary scan. the arm cortex-m0+ is configured to support up to four breakpoints and two watch points. the micro trace buffer is implemented on the lpc82x. the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd debug port is disabled while the lpc82x is in reset. the jtag boundary scan pins are selected by hardware when the part is in boundary scan mode on pins pio0_0 to pio0_3 (see table 3 ). to perform boundary scan testing, follow these steps: 1. erase any user code residing in flash. 2. power up the part with the reset pin pulled high externally. 3. wait for at least 250 ? s. 4. pull the reset pin low externally. 5. perform boundary scan operations. 6. once the boundary scan operations are completed, assert the trst pin to enable the swd debug mode, and release the reset pin (pull high). remark: the jtag interface cannot be used for debug purposes. fig 11. connecting the swd pins to a standard swd connector reset swdio swclk v dd lpc82x isp entry pio0_12 vtref swdio swclk nreset gnd aaa-015075 from swd connector 3.3 v ~10 k - 100 k dgnd ~10 k - 100 k lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 31 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 9. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] maximum/minimum voltage above the maximum operating voltage (see table 8 ) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. failure includes the loss of reli ability and shorter lifetime o f the device. [3] applies to all 5 v tolerant i/o pins except true open-drain pins pio0_10 and pio0_11 and except the 3 v tolerant pin pio0_6. [4] including the voltage on outputs in 3-state mode. [5] v dd present or not present. compliant with the i 2 c-bus standard. 5.5 v can be applied to this pin when v dd is powered down. [6] v dd present or not present. [7] an adc input voltage above 3.6 v can be applied for a short ti me without leading to immediate, unrecoverable failure. accumu lated exposure to elevated voltages at 4.6 v must be less than 10 6 s total over the lifetime of the device. applying an elevated voltage to the adc inputs for a long time affects the reliabili ty of the device and reduces its lifetime. [8] if the comparator is configured with the common mode input v ic = v dd , the other comparator input can be up to 0.2 v above or below v dd without affecting the hysteresis range of the comparator function. [9] it is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [10] dependent on package type. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) [2] ? 0.5 +4.6 v v ref reference voltage on pin vrefp ? 0.5 v dd v v i input voltage 5 v tolerant i/o pins; v dd ? 1.8 v [3] [4] ? 0.5 +5.5 v on i2c open-drain pins pio0_10, pio0_11 [5] ? 0.5 +5.5 v 3 v tolerant i/o pin pio0_6 [6] ? 0.5 +3.6 v v ia analog input voltage [7] [8] [9] ? 0.5 +4.6 v v i(xtal) crystal input voltage [2] ? 0.5 +2.5 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ?c - 100 ma t stg storage temperature [10] ? 65 +150 ?c t j(max) maximum junction temperature - 150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [11] - 3500 v charged device model; hvqfn33 package - 1200 v lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 32 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [11] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. 10. thermal characteristics the average chip junction temperature, t j ( ? c), can be calculated using the following equation: (1) ? t amb = ambient temperature ( ? c), ? r th(j-a) = the package junction-to-ambient thermal resistance ( ? c/w) ? p d = sum of internal and i/o power dissipation the internal power dissipation is the product of i dd and v dd . the i/o power dissipation of the i/o pins is often small and many times can be negligible. however it can be significant in some applications. table 6. thermal resistance symbol parameter conditions max/min unit hvqfn33 package r th(j-a) thermal resistance from junction-to-ambient jedec (4.5 in ? 4 in); still air 40 +/- 15 % ?c/w single-layer (4.5 in ? 3 in); still air 114 +/- 15 % ?c/w r th(j-c) thermal resistance from junction-to-case 18 +/- 15 % ?c/w t j t amb p d r th j a ? ?? ? ?? += lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 33 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 11. static characteristics 11.1 general operating conditions [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. [2] including bonding pad capacitance. bas ed on simulation, not tested in production. table 7. general operating conditions t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit f clk clock frequency internal cpu/system clock - - 30 mhz v dd supply voltage (core and external rail) 1.8 3.3 3.6 v v ref reference voltage on pin vrefp 2.4 - v dd v oscillator pins v i(xtal) crystal input voltage on pin xtalin ? 0.5 1.8 1.95 v v o(xtal) crystal output voltage on pin xtalout ? 0.5 1.8 1.95 v pin capacitance c io input/output capacitance pins with analog and digital functions [2] -- 7.1pf i 2 c-bus pins (pio0_10 and pio0_11) [2] - - 2.5 pf pins with digital functions only [2] -- 2.8pf lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 34 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 11.2 supply pins table 8. static characteristics, supply pins t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit i dd supply current active mode; code while(1){} executed from flash; system clock = 12 mhz; default mode; v dd = 3.3 v [2] [3] [4] [6] [7] -1.85-ma system clock = 12 mhz; low-current mode; v dd = 3.3 v [2] [3] [4] [6] [7] -1.04-ma system clock = 30 mhz; default mode; v dd = 3.3 v [2] [3] [6] [7] [9] -3.95-ma system clock = 30 mhz; low-current mode; v dd = 3.3 v [2] [3] [6] [7] [9] -3.2-ma sleep mode system clock = 12 mhz; default mode; v dd = 3.3 v [2] [3] [4] [6] [7] -1.35-ma system clock = 12 mhz; low-current mode; v dd = 3.3 v [2] [3] [4] [6] [7] -0.8-ma system clock = 30 mhz; default mode; v dd = 3.3 v [2] [3] [9] [6] [7] -2.55-ma system clock = 30 mhz; low-current mode; v dd = 3.3 v [2] [3] [9] [6] [7] -2.1-ma i dd supply current deep-sleep mode; v dd = 3.3 v; t amb =25 ?c [2] [3] [10] - 158 300 ? a t amb =105 ?c - - 400 ? a i dd supply current power-down mode; v dd = 3.3 v t amb =25 ?c [2] [3] [10] - 1.6 10 ? a t amb =105 ?c- - 5 0 ? a i dd supply current deep power-down mode; v dd = 3.3 v; 10 khz low-power oscillator and self-wake-up timer (wkt) disabled t amb =25 ?c [2] [11] -0.21 ? a t amb =105 ?c- - 4 ? a lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 35 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. [2] t amb =25 ? c. [3] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [4] irc enabled; system oscillator disabled; system pll disabled. [5] system oscillator enabled; i rc disabled; system pll disabled. [6] bod disabled. [7] all peripherals disabled in the sysahbclkctrl register. peri pheral clocks to usart, clkout, and iocon disabled in system configuration block. [8] irc enabled; system oscillator disabled; system pll enabled. [9] irc disabled; system oscill ator enabled; system pll enabled. [10] all oscillators and analog blocks turned off. [11] wakeup pin pulled high externally. i dd supply current deep power-down mode; v dd = 3.3 v; 10 khz low-power oscillator and self-wake-up timer (wkt) enabled -1.1- ? a deep power-down mode; v dd = 3.3 v; external clock input wktclkin @ 10 khz with self-wake-up timer enabled -0.4- ? a deep power-down mode; v dd = 3.3 v; external clock input wktclkin @ 32 khz with self-wake-up timer enabled -0.7- ? a table 8. static characteristics, supply pins ?continued t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 36 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 11.3 electrical pin characteristics table 9. static characteristics, electrical pin characteristics t amb = ? 40 ? c to +105 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit standard port pins configured as digital pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.510 [2] na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.510 [2] na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510 [2] na v i input voltage v dd ? 1.8 v; 5 v tolerant pins except pio0_12 [4] [6] 0- 5v v dd = 0 v 0 - 3.6 v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage i oh = 4 ma; 2.5 v <= v dd <= 3.6 v v dd ? 0.4 - - v i oh = 3 ma; 1.8 v <= v dd < 2.5 v v dd ? 0.4 - - v v ol low-level output voltage i ol = 4 ma; 2.5 v <= v dd <= 3.6 v - - 0.4 v i ol = 3 ma; 1.8 v <= v dd < 2.5 v - - 0.4 v i oh high-level output current v oh =v dd ? 0.4 v; 2.5 v ? v dd ? 3.6 v 4- -ma 1.8 v ? v dd < 2.5 v 3 - - ma i ol low-level output current v ol =0.4v 2.5 v ? v dd ? 3.6 v 4- -ma 1.8 v ? v dd < 2.5 v 3 - - ma i ohs high-level short-circuit output current v oh =0v [7] -- 45ma i ols low-level short-circuit output current v ol =v dd [7] -- 50ma i pd pull-down current v i = 5 v 10 50 150 ? a i pu pull-up current v i =0v; 2.0 v ? v dd ? 3.6 v 15 50 85 ? a 1.8 v ? v dd < 2.0 v 10 50 85 v dd lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 39 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 11.4 power consumption power measurements in active, sleep, deep-sleep, and power-down modes were performed under the following conditions: ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpio dir register. ? write 1 to the gpio clr register to drive the outputs low. conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regi ster (sysahbclkctrl =0x1f); all peripheral clocks disabled; internal pull-up resistors disabled; bod disabled; low-current mode. 1 mhz - 6 mhz: external clock; irc, pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz: irc enabled; pll enabled. 30 mhz: system oscillator enabled; pll enabled. fig 13. active mode: typical supply current i dd versus supply voltage v dd aaa-013992 1.8 2.4 3 3.6 0 1 2 3 4 v dd (v) i dd dd i dd (ma) (ma) (ma) 30 mhz 30 mhz 30 mhz 24 mhz 24 mhz 24 mhz 12 mhz 12 mhz 12 mhz 6 mhz 6 mhz 6 mhz 4 mhz 4 mhz 4 mhz 3 mhz 3 mhz 3 mhz 2 mhz 2 mhz 2 mhz 1 mhz 1 mhz 1 mhz lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 40 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; all peripherals disabled in the sysahbclkctrl regi ster (sysahbclkctrl =0x1f); all peripheral clocks disabled; internal pull-up resistors disabled; bod disabled; low-current mode. 1 mhz - 6 mhz: external clock; irc, pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz: irc enabled; pll enabled. 30 mhz: system oscillator enabled; pll enabled. fig 14. active mode: typical supply current i dd versus temperature aaa-013993 -40 10 60 110 0 1 2 3 4 temperature (c) i dd dd i dd (ma) (ma) (ma) 30 mhz 30 mhz 30 mhz 24 mhz 24 mhz 24 mhz 12 mhz 12 mhz 12 mhz 6 mhz 6 mhz 6 mhz 4 mhz 4 mhz 4 mhz 3 mhz 3 mhz 3 mhz 2 mhz 2 mhz 2 mhz 1 mhz 1 mhz 1 mhz lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 41 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 3.3 v; sleep mode entered from fl ash; all peripheral s disabled in the sysahbclkctrl register (sysahbclk ctrl =0x1f); all peripheral clocks disabled; internal pull-up resistors disabled; bo d disabled; low-current mode. 1 mhz - 6 mhz: external clock; irc, pll disabled. 12 mhz: irc enabled; pll disabled. 24 mhz: irc enabled; pll enabled. 30 mhz: system oscillator enabled; pll enabled. fig 15. sleep mode: typical supply current i dd versus temperature for different system clock frequencies conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 16. deep-sleep mode: typical supply current i dd versus temperature for different supply voltages v dd aaa-013994 -40 10 60 110 0 0.5 1 1.5 2 2.5 temperature (c) i dd dd i dd (ma) (ma) (ma) 30 mhz 30 mhz 30 mhz 24 mhz 24 mhz 24 mhz 12 mhz 12 mhz 12 mhz 6 mhz 6 mhz 6 mhz 4 mhz 4 mhz 4 mhz 3 mhz 3 mhz 3 mhz 2 mhz 2 mhz 2 mhz 1 mhz 1 mhz 1 mhz aaa-013983 -40 -10 20 50 80 110 120 130 140 150 160 170 180 temperature (c) i dd dd i dd (ua) (ua) (a) 3.6 v 3.6 v v dd = 3.6 v 3.3 v 3.3 v 3.3 v 2.7 v 2.7 v 2.7 v 2 v 2 v 2 v 1.8 v 1.8 v 1.8 v lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 42 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller conditions: bod disabled; all oscillators and analog blocks disabled in the pdsleepcfg register (pdsleepcfg = 0x0000 18ff). fig 17. power-down mode: typical supply current i dd versus temperature for different supply voltages v dd wkt not running. fig 18. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd aaa-013984 -40 -10 20 50 80 110 0 5 10 15 20 25 temperature (c) i dd dd i dd (a) (a) (a) vdd = 3.6 v vdd = 3.6 v v dd = 3.6 v 3.3 v 3.3 v 3.3 v 1.8 v 1.8 v 1.8 v aaa-013985 -40 -10 20 50 80 110 0 0.5 1 1.5 2 temperature (c) i dd dd i dd (ua) (ua) (a) v dd = 3.6 v 3.3 v 2.7 v 1.8 v lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 43 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller wkt running with internal 10 khz low-power oscillator. fig 19. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (internal clock) wkt running with external 10 khz clock. clock inpu t waveform: square wave with rise time and fall time of 5 ns. fig 20. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (external 10 khz input clock) aaa-013991 -40 -10 20 50 80 110 0 0.5 1 1.5 2 2.5 3 temperature (c) i dd dd i dd (a) (a) (a) 3.6 3.6 3.3 3.3 3.3 v 2.4 2.4 1.8 1.8 1.8 v v dd = 3.6 v 2.4 v aaa-014386 -40 -10 20 50 80 110 0 0.5 1 1.5 2 temperature (c) i dd dd i dd (a) (a) (a) vdd = 3.6 v vdd = 3.6 v v dd = 3.6 v 3.3 v 3.3 v 3.3 v 2.7 v 2.7 v 2.7 v 1.8 v 1.8 v 1.8 v lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 44 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller wkt running with external 32 khz clock. clock inpu t waveform: square wave with rise time and fall time of 5 ns. fig 21. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (external 32 khz input clock) wkt running with external 1 mhz clock. clock input waveform: square wave with rise time and fall time of 5 ns. fig 22. deep power-down mode: typical supply current i dd versus temperature for different supply voltages v dd (external 1 mhz input clock) aaa-014388 -40 -10 20 50 80 110 0 0.5 1 1.5 2 2.5 3 temperature (c) i dd dd i dd (a) (a) (a) vdd = 3.6 v vdd = 3.6 v v dd = 3.6 v 3.3 v 3.3 v 3.3 v 2.7 v 2.7 v 2.7 v 1.8 v 1.8 v 1.8 v aaa-014389 -40 -10 20 50 80 110 0 5 10 15 20 25 temperature (c) i dd dd i dd (a) (a) (a) 1.8 v 1.8 v 1.8 v 2.7 v 2.7 v 2.7 v 3.3 v 3.3 v 3.3 v vdd = 3.6 v vdd = 3.6 v vdd = 3.6 v lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 45 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 11.5 coremark data conditions: v dd = 3.3 v; t amb = 25 c; active mode; all periphe rals except one uart and the sct disabled in the sysahbclkctrl register; bod di sabled; internal pull-up resistors enabled. measured with keil uvision 5.10. 1 mhz - 6 mhz: external clock; irc, pll di sabled.12 mhz: irc enabled; pll disabled. 24 mhz: irc enabled; pll enabled.30 mhz: system oscillator enabled; pll enabled. fig 23. coremark score conditions: v dd = 3.3 v; t amb = 25 c; active mode; all periphe rals except one uart and the sct disabled in the sysahbclkctrl register; bod di sabled; internal pull-up resistors enabled. measured with keil uvision 5.10. 1 mhz - 6 mhz: external clock; irc, pll di sabled.12 mhz: irc enabled; pll disabled.24 mhz: irc enabled; pll enabled.30 mhz: system oscillator enabled; pll enabled. fig 24. active mode: coremark power consumption i dd aaa-014006 0 6 12 18 24 30 0 0.5 1 1.5 2 2.5 system clock frequency (mhz) coremark score coremark score coremark score ((iterations/s)/mhz) ((iterations/s)/mhz) ((iterations/s)/mhz) default default default cpu/ef ficiency cpu/ef ficiency low-current low-current low-current cpu performance/efficiency aaa-014007 0 6 12 18 24 30 0 2 4 6 8 system clock frequency (mhz) i dd dd i dd (ma) (ma) (ma) default default default cpu/efficiency cpu/efficiency low-current low-current low-current cpu performance/efficiency lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 46 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 11.6 peripheral power consumption the supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the sysahbclkcfg. and pdruncfg (for analog blocks) registers. all other blocks are disabled in both registers and no code accessing the periphe ral is executed. measured on a typical sample at t amb =25 ? c. unless noted otherwise, th e system oscillator and pll are running in both measurements. the supply currents are shown for system clock frequencies of 12 mhz and 30 mhz. table 10. power consumption for indi vidual analog and digital blocks peripheral typical supply current in a notes main clock frequency = n/a 12 mhz 30 mhz irc 261 - - system oscillator running; pll off; independent of main clock frequency; irc output disabled. system oscillator at 12 mhz 274 - - irc r unning; pll off; independent of main clock frequency. watchdog oscillator 2 - - system oscillator running; pll off; independent of main clock frequency. bod 39 - - independent of main clock frequency. main pll - 301 - - clkout - 67 150 main clock divided by 4 in the clkoutdiv register. rom - 27 68 - gpio + pin interrupt/pattern match - 95 233 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabl ed in the sysahbclkcfg register. swm - 59 145 - iocon - 45 110 - sctimer/pwm - 168 411 - mrt - 89 220 - wwdt - 29 71 - i2c0 - 54 132 - i2c1 - 49 122 - i2c2 - 52 127 - i2c3 - 57 142 - spi0 - 55 136 - spi1 - 55 136 - usart0 - 50 124 - usart1 - 54 134 - usart2 - 56 138 - comparator acmp - 34 82 - lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 47 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 11.7 electrical pin characteristics adc - 57 141 digital controller only. analog portion of the adc disabled in the pdruncfg register. - 57 141 combined analog and digital logic. adc enabled in the pdruncfg register and lpwrmode bit set to 1 in the adc ctrl register (adc in low-power mode). - 1990 2070 combined analog and digital logic. adc enabled in the pdruncfg register and lpwrmode bit set to 0 in the adc ctrl register (adc powered). dma - 324 793 crc - 34 85 - table 10. power consumption for indi vidual analog and digital blocks ?continued peripheral typical supply current in a notes main clock frequency = n/a 12 mhz 30 mhz conditions: v dd = 1.8 v; on pin pio0_12. conditions: v dd = 3.3 v; on pin pio0_12. fig 25. high-drive output: typical high-level output voltage v oh versus high-level output current i oh aaa-013973 0 4 8 12 16 20 24 1.2 1.3 1.4 1.5 1.6 1.7 1.8 i oh (ma) v ol ol v oh (v) (v) (v) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c aaa-013974 0 20 40 60 80 2 2.3 2.6 2.9 3.2 3.5 i oh (ma) v ol ol v oh (v) (v) (v) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 48 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 1.8 v; on pins pio0_10 and pio0_11. conditions: v dd = 3.3 v; on pins pio0_10 and pio0_11. fig 26. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol aaa-013964 0 0.1 0.2 0.3 0.4 0.5 0.6 0 10 20 30 40 v ol (v) i ol ol i ol (ma) (ma) (ma) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c aaa-013972 0 0.1 0.2 0.3 0.4 0.5 0.6 0 15 30 45 60 v ol (v) i ol ol i ol (ma) (ma) (ma) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c conditions: v dd = 1.8 v; standard port pins and high-drive pin pio0_12. conditions: v dd = 3.3 v; standard port pins and high-drive pin pio0_12. fig 27. typical low-level output current i ol versus low-level output voltage v ol aaa-013975 0 0.1 0.2 0.3 0.4 0.5 0.6 0 2 4 6 8 10 v ol (v) i ol ol i ol (ma) (ma) (ma) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c aaa-013976 0 0.1 0.2 0.3 0.4 0.5 0.6 0 3 6 9 12 15 v ol (v) i ol ol i ol (ma) (ma) (ma) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 49 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller conditions: v dd = 1.8 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 28. typical high-level output voltage v oh versus high-level output source current i oh aaa-013977 0 1.5 3 4.5 6 1.2 1.3 1.4 1.5 1.6 1.7 1.8 i oh (ma) v oh oh v oh (v) (v) (v) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c aaa-013978 0 8 16 24 2 2.3 2.6 2.9 3.2 3.5 i oh (ma) v oh oh v oh (v) (v) (v) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c conditions: v dd = 1.8 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 29. typical pull-up current i pu versus input voltage v i aaa-013979 0 0.7 1.4 2.1 2.8 3.5 -16 -12 -8 -4 0 v i (v) i pu pu i pu (ua) (ua) (a) -40 c -40 c -40 c 105 c 105 c 105 c 90 c 90 c 90 c 25 c 25 c 25 c aaa-013980 0 1 2 3 4 5 -70 -56 -42 -28 -14 0 v i (v) i pu pu i pu (ua) (ua) (a) 105 c 105 c 105 c -40 c -40 c -40 c 90 c 90 c 90 c 25 c 25 c 25 c lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 50 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 12. dynamic characteristics 12.1 flash/eeprom memory [1] number of program/erase cycles. [2] programming times are given for writing 64 bytes to the flash. t amb <= +85 ? c. flash programming with iap calls (see lpc82x user manual ). 12.2 external clock for th e oscillator in slave mode remark: the input voltage on the xtalin and xtalout pins must be ? 1.95 v (see ta b l e 8 ). for connecting the oscillato r to the xtal pins, also see section 12.2 . conditions: v dd = 1.8 v; standard port pins. conditions: v dd = 3.3 v; standard port pins. fig 30. typical pull-down current i pd versus input voltage v i aaa-013981 0 0.7 1.4 2.1 2.8 3.5 0 7 14 21 28 35 v i (v) i pu pu i pd (ua) (ua) (a) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c aaa-013982 0 1 2 3 4 5 0 20 40 60 80 v i (v) i pd pd i pd (ua) (ua) (a) -40 c -40 c -40 c 25 c 25 c 25 c 90 c 90 c 90 c 105 c 105 c 105 c table 11. flash characteristics t amb = ? 40 ? c to +105 ? c. based on jedec nvm qualification. failure rate < 10 ppm for parts as specified below. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 20 - years not powered 20 40 - years t er erase time page or multiple consecutive pages, sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 51 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. 12.3 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are for room temperature (25 ? c), nominal supply voltages. table 12. dynamic characteristic : external clock (xtalin input) t amb = ? 40 ? c to +105 ? c; v dd over specified ranges. [1] symbol parameter min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns fig 31. external clock timing (with an amplitude of at least v i(rms) = 200 mv) w & + & / w & / & ; w & + & ; 7 f \ f o n w & / & + w & + & / w & / & ; w & + & ; 7 f \ f o n w & / & + w & + & / w & / & ; w & + & ; 7 f \ f o n w & / & + w & + & / w & / & ; w & + & ; 7 f \ f o n w & / & + d d d table 13. dynamic char acteristics: irc t amb = ? 40 ? c to +105 ? c; 2.7 v ? v dd ? 3.6 v [1] . symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.82 12 12.18 mhz lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 52 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [1] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +105 ? c) is ? 40 %. [3] see the lpc82x user manual. conditions: frequency values are typical values. 12 mhz ? 1.5 % accuracy is guaranteed for 2.7 v ? v dd ? 3.6 v. variations between parts may cause the irc to fall outside the 12 mhz ? 1.5 % accuracy specification for voltages below 2.7 v. fig 32. typical internal rc oscillator frequency versus temperature table 14. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4-khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz aaa-014008 -40 -10 20 50 80 110 11.8 11.9 12 12.1 12.2 temperature (c) f f (mhz) (mhz) (mhz) 3.6 v 3.6 v v dd = 3.6 v 3.3 v 3.3 v 3.3 v 3 v 3 v 3 v 2.7 v 2.7 v 2.7 v 2.4 v 2.4 v 2.4 v 2.1 v 2.1 v 2.1 v 2 v 2 v 2 v 1.8 v 1.8 v 1.8 v lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 53 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 12.3.1 i/o pins [1] applies to standard port pins and reset pin. 12.3.2 wktclkin pin (wake-up clock input) [1] assuming a square-wave input clock. 12.3.3 sctimer/pwm output timing 12.3.4 i 2 c-bus table 15. dynamic characteristics: i/o pins [1] t amb = ? 40 ? c to +105 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 16. dynamic characte ristics: wktclkin pin t amb = ? 40 ? c to +105 ? c; 1.8 v ? v dd ? 3.6 v. symbol parameter conditions min max unit f clk clock frequency deep power-down mode and power-down mode [1] -1 mhz deep-sleep, sleep, and active mode [1] -10mhz t chcx clock high time - 50 - ns t clcx clock low time - 50 - ns table 17. sctimer/pwm output dynamic characteristics t amb = ? 40 ? c to 105 ? c; 2.4 v <= v dd <= 3.6 v; c l = 10 pf. simulated skew (over process, voltage, and temperature) of any two sct output signals routed to standard i/o pins; sampled at the 50 % level of the falling or rising edge; values guaranteed by design. symbol parameter conditions min typ max unit t sk(o) output skew time - - - 4 ns table 18. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c; values guaranteed by design. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus; on pins pio0_10 and pio0_11 01mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode - 300 ns fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus; on pins pio0_10 and pio0_11 - 120 ns lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 54 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating temp erature range unless otherwise specified. [3] t hd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowledge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for both output stage and bus timing. if series resistors are used, designers should allow for this when considering bus timing. [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if the device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] t su;dat is the data set-up time that is measured with res pect to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low per iod of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. also the acknowledge timing must meet this set-up time. t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus; on pins pio0_10 and pio0_11 0- ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus; on pins pio0_10 and pio0_11 50 - ns table 18. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +105 ? c; values guaranteed by design. [2] symbol parameter conditions min max unit lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 55 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller fig 33. i 2 c-bus pins clock timing d d d w i 6 ' $ w i 6 w + ' ' $ 7 6 & / i 6 & / w 9 ' ' $ 7 w + , * + w / 2 : w 6 8 ' $ 7 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 56 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 12.3.5 spi interfaces in master mode, the maximum supported bit ra te is limited by the maximum system clock to 30 mbit/s. in slave mode, assuming a set-up time of 3 ns for the external device and neglecting any pcb trace delays, the maximum supported bit rate is 1/(2 x (26 ns + 3 ns)) = 17 mbit/s at 3.0 v <= vdd <= 3.6 v and 13 mbit/s at 1.8 v <= vdd < 3.0 v. the actual bit rate depends on the delays introduced by the external trace and the external device. remark: spi functions can be assigned to all digita l pins. the characteristics are valid for all digital pins except the open-drain pins pio0_10 and pio0_11. table 19. spi dynamic characteristics t amb = ? 40 ? c to 105 ? c; c l = 20 pf; input slew = 1 ns. simulated parameters sampled at the 30 % and 70 % level of the rising or falling edge; values guaranteed by design. delays introduced by the external trace or external device are not considered. symbol parameter conditions min max unit spi master t ds data set-up time 1.8 v <= v dd <= 3.6 v 2 - ns t dh data hold time 1.8 v <= v dd <= 3.6 v 6 - ns t v(q) data output valid time 1.8 v <= v dd <= 3.6 v -3 4 ns spi slave t ds data set-up time 1.8 v <= v dd <= 3.6 v 2 - ns t dh data hold time 1.8 v <= v dd <= 3.6 v 4 - ns t v(q) data output valid time 3.0 v <= v dd <= 3.6 v 0 26 ns 1.8 v <= v dd < 3.0 v 0 35 ns lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 57 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller t cy(clk) = cclk/divval with cclk = system clock frequency. divval is the spi clock divider. see the lpc82x user manual . fig 34. spi master timing sck (cpol = 0) mosi (cpha = 1) ssel miso (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid mosi (cpha = 0) miso (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014969 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb) lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 58 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller fig 35. spi slave timing sck (cpol = 0) miso (cpha = 1) ssel mosi (cpha = 1) t cy(clk) t ds t dh t v(q) data valid (lsb) data valid t v(q) sck (cpol = 1) data valid (lsb) data valid miso (cpha = 0) mosi (cpha = 0) t ds t dh data valid (msb) data valid (msb) data valid data valid (lsb) data valid (lsb) t v(q) data valid (msb) data valid t v(q) aaa-014970 data valid (msb) data valid (msb) data valid (msb) data valid (msb) idle idle idle idle data valid (msb) lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 59 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 12.3.6 usart interface the maximum usart bit rate is 10 mbit/s in synchronous mode master mode and 10 mbit/s in synchronous slave mode. remark: usart functions can be assigned to all di gital pins. the characteristics are valid for all digital pins except the ope n-drain pins pio0_10 and pio0_11. table 20. usart dynamic characteristics t amb = ? 40 ? c to 105 ? c; 1.8 v <= v dd <= 3.6 v unless noted otherwise; c l = 10 pf; input slew = 10 ns. simulated parameters sampled at the 30 %/70 % level of the falling or rising edge; values guaranteed by design. symbol parameter conditions min max unit usart master (in synchronous mode) t su(d) data input set-up time 3.0 v <= v dd <= 3.6 v 31 - ns 1.8 v <= v dd < 3.0 v 37 t h(d) data input hold time 0 - ns t v(q) data output valid time 0 5 ns usart slave (in synchronous mode) t su(d) data input set-up time 6 - ns t h(d) data input hold time 2 - ns t v(q) data output valid time 3.0 v <= v dd <= 3.6 v 0 28 ns 1.8 v <= v dd < 3.0 v 0 37 ns in master mode, t cy(clk) = u_pclk/brgval. see the lpc82x user manual . fig 36. usart timing un_sclk (clkpol = 0) txd rxd t cy(clk) t su(d) t h(d) t v(q) t v(q) start bit0 un_sclk (clkpol = 1) start bit0 bit1 bit1 aaa-015074 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 60 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 13. characteristics of analog peripherals 13.1 bod [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see the lpc82x user manual . interrupt level 0 is reserved. table 21. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 1 assertion - 2.25 - v de-assertion - 2.40 - v interrupt level 2 assertion - 2.54 - v de-assertion - 2.68 - v interrupt level 3 assertion - 2.85 - v de-assertion - 2.95 - v reset level 0 assertion - 1.46 - v de-assertion - 1.61 - v reset level 1 assertion - 2.05 - v de-assertion - 2.20 - v reset level 2 assertion - 2.34 - v de-assertion - 2.49 - v reset level 3 assertion - 2.63 - v de-assertion - 2.78 - v lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 61 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 13.2 adc [1] the input resistance of adc channel 0 is higher than for all other channels. see figure 37 . [2] in the adc trm register, set vrange = 0 (default). [3] in the adc trm register, set vrange = 1 (default). [4] based on characterization. not tested in production. [5] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 38 . [6] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 38 . [7] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 38 . [8] the full-scale error voltage or gain error (e g ) is the difference between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 38 . [9] t amb = 25 ? c; maximum sampling frequency f s = 2 msamples/s and analog input capacitance c ia = 0.1 pf. [10] input impedance z i is inversely proportional to the sampling fr equency and the total input capacity including c ia and c io : z i ? 1 / (f s ? c i ). see table 8 for c io . table 22. 12-bit adc static characteristics t amb = ? 40 ? c to +105 ? c unless noted otherwise; v dd = 2.4 v to 3.6 v; vrefp = v dd ; vrefn = v ss . symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd v v ref reference voltage on pin vrefp 2.4 - v dd v c ia analog input capacitance - - 0.32 pf f clk(adc) adc clock frequency 2.7 v <= v dd <= 3.6 v [2] -- 30mhz 2.4 v <= v dd < 2.7 v [3] -- 25mhz f s sampling frequency 2.7 v <= v dd <= 3.6 v [2] - - 1.2 msamples/s 2.4 v <= v dd < 2.7 v [3] - - 1 msamples/s e d differential linearity error t amb = 105 c [5][4] - +/- 2.5 - lsb e l(adj) integral non-linearity t amb = 105 c [6][4] - +/- 2.5 - lsb e o offset error t amb = 105 c [7][4] - +/- 4.5 - lsb v err(fs) full-scale error voltage 1.2 msamples/s; t amb = 105 c [8][4] - +/- 0.5 - % z i input impedance f s = 1.2 msamples/s [1][9] [10] 0.1 - - m ? lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 62 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller fig 37. adc input impedance dac adc r sw = 5 ...25 r 1 = 0.25 k...2.5 k c ia c dac adcn_0 adcn_[1:11] aaa-011748 c io c io lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 63 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 38. 12-bit adc characteristics 002aaf436 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp - v ss 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb = lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 64 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 13.3 comparator and internal voltage reference table 23. internal voltage reference static and dynamic characteristics t amb = ? 40 ? c to +105 ? c; v dd = 3.3 v; hysteresis disabled in the comparator ctrl register. symbol parameter conditions min typ max unit v o output voltage t amb = 25 ? c to 105 ? c 860 - 940 mv t amb = 25 ?c 904 mv v dd = 3.3 v; characterized through bench measurements on typical samples. fig 39. typical internal voltage reference output voltage aaa-014424 -40 -10 20 50 80 110 0.890 0.895 0.900 0.905 0.910 temperature (c) v ref ref v o (mv) (mv) (v) table 24. comparator characteristics t amb = ? 40 ? c to +105 ? c unless noted otherwise; v dd = 1.8 v to 3.6 v. symbol parameter conditions min typ max unit static characteristics v ref(cmp) comparator reference voltage pin pio0_6/vddcmp configured for function vddcmp 1.5 - 3.6 v i dd supply current vp > vm; t amb = 25 c; v dd = 3.3 v [2] -90 - ? a vm > vp; t amb = 25 c; v dd = 3.3 v [2] -60 - ? a v ic common-mode input voltage 0 - v dd v dv o output voltage variation 0 - v dd v v offset offset voltage v ic = 0.1 v; v dd = 2.4 v; t amb = 105 c [2] -+/- 4- mv v ic = 1.5 v; v dd = 2.4 v; t amb = 105 c [2] -+/- 2- mv v ic = 2.9 v; v dd = 2.4 v; t amb = 105 c [2] -+/- 4- mv dynamic characteristics t startup start-up time nominal process; v dd = 3.3 v; t amb = 25 c -13 - ? s lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 65 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [1] c l = 10 pf [2] characterized on typical samp les, not tested in production. [3] input hysteresis is relative to the referenc e input channel and is software programmable. [4] 100 mv overdrive corresponds to a square wave from 50 mv below the reference (v ic ) to 50 mv above the reference. [1] characterized on typical samples, not tested in production. t pd propagation delay high to low; v dd = 3.0 v; t amb = 105 c v ic = 0.1 v; 100 mv overdrive input [1][2][4] - 140 - ns v ic = 0.1 v; rail-to-rail input [1][2] - 190 - ns v ic = 1.5 v; 100 mv overdrive input [1][2][4] - 130 - ns v ic = 1.5 v; rail-to-rail input [1][2] - 120 - ns v ic = 2.9 v; 100 mv overdrive input [1][2][4] - 220 - ns v ic = 2.9 v; rail-to-rail input [1][2] -80 - ns t pd propagation delay low to high; v dd = 3.0 v; t amb = 105 c v ic = 0.1 v; 100 mv overdrive input [1][2][4] - 240 - ns v ic = 0.1 v; rail-to-rail input [1][2] -60 - ns v ic = 1.5 v; 100 mv overdrive input [1][2][4] - 160 - ns v ic = 1.5 v; rail-to-rail input [1][2] - 150 - ns v ic = 2.9 v; 100 mv overdrive input [1][2][4] - 150 - ns v ic = 2.9 v; rail-to-rail input [1][2] - 260 - ns v hys hysteresis voltage positive hysteresis; v dd = 3.0 v; v ic = 1.5 v; t amb = 105 c; settings: 5 mv [3] - 6 - mv 10 mv - 11 - mv 20 mv - 23 - mv v hys hysteresis voltage negative hysteresis; v dd = 3.0 v; v ic = 1.5 v; t amb = 105 c; settings: 5 mv [1][3] -10 - mv 10 mv - 15 - mv 20 mv - 27 - mv r lad ladder resistance - - 1 - m ? table 24. comparator characteristics ?continued t amb = ? 40 ? c to +105 ? c unless noted otherwise; v dd = 1.8 v to 3.6 v. symbol parameter conditions min typ max unit table 25. comparator voltage ladder dynamic characteristics t amb = ? 40 ? c to +105 ? c; v dd = 1.8 v to 3.6 v. symbol parameter conditions min typ max unit t s(pu) power-up settling time to 99% of voltage ladder output value [1] -1 7- ? s t s(sw) switching settling time to 99% of voltage ladder output value [1] -1 8- ? s lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 66 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller [1] characterized though limited samples. not tested in production. [2] all peripherals except comparator, temperature sensor, and irc turned off. table 26. comparator voltage ladder reference static characteristics v dd = 1.8 v to 3.6 v. t amb = -40 ? c to + 105 ? c; external or internal reference. symbol parameter conditions min typ [1] max unit e v(o) output voltage error decimal code = 00 [2] - +/- 6 - mv decimal code = 08 - +/- 1 - % decimal code = 16 - +/- 1 - % decimal code = 24 - +/- 1 - % decimal code = 30 - +/- 1 - % decimal code = 31 - +/- 1 - % lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 67 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 14. application information 14.1 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended to couple the input through a capacitor with c i = 100 pf. to limit the input voltage to the specif ied range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. in slave mode the input clock signal should be coupled with a capacitor of 100 pf ( figure 40 ), with an amplitude between 200 mv (rms) and 1000 mv (rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 41 and in ta b l e 2 7 and ta b l e 2 8 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 must be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by l, c l and r s ). capacitance c p in figure 41 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer (see ta b l e 2 7 ). fig 40. slave mode operation of the on-chip oscillator / 3 & ; 7 $ / , 1 & l s ) & j d d d lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 68 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 14.2 xtal printed-circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 ,c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in fig 41. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 27. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz to 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf 5 mhz to 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz to 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz to 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 28. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz to 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz to 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf d d d / 3 & ; 7 $ / , 1 ; 7 $ / 2 8 7 & ; & ; ; 7 $ / & / & 3 5 6 / lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 69 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller according to the increase in parasitics of the pcb layout. 14.3 connecting power, clo cks, and debug functions figure 42 shows the basic board connections used to power the lpc82x, connect the external crystal, and pr ovide debug capabilities vi a the serial wire port. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 70 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 14.4 termination of unused pins ta b l e 2 9 shows how to terminate pins that are not used in the application. in many cases, unused pins may should be connected externally or configured correctly by software to minimize the overall power consumption of the part. (1) see section 14.1 ? xtal input ? for the values of c1 and c2. (2) position the decoupling capacitors of 0.1 f and 0.01 f as close as possible to the v dd pin. add one set of decoupling capacitors to each v dd pin. (3) position the decoupling capacitors of 0.1 f as close as possible to the vrefn and v dd pins. the 10 f bypass capacitor filters the power line. tie vrefp to v dd if the adc is not used. tie vrefn to v ss if adc is not used. (4) uses the arm 10-pin interface for swd. (5) when measuring signals of low frequency, use a low-pass filter to remove noise and to improve adc performance. also see ref. 4 . fig 42. power, clock, and debug connections swdio/pio0_2 swclk/pio0_3 reset/pio0_5 v ss v ssa pio0_12 adc_0 pio0_8/xtalin pio0_9/xtalout v dd (2 to 5 pins) vrefp pio0_6/adc_1/vddcmp vrefn lpc82x 3.3 v 3.3 v dgnd dgnd dgnd dgnd agnd 1 3 5 7 9 2 4 6 8 10 note 4 note 5 note 5 (adc_1), note 3 (vddcmp) c1 c2 note 1 dgnd dgnd note 2 note 3 0.01 f 0.1 f 3.3 v agnd agnd agnd 10 f 0.1 f 0.1 f isp select pin n.c. n.c. n.c. swd connector 3.3 v ~10 k - 100 k ~10 k - 100 k aaa-015073 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 71 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller unused pins with gpio function should be configured as outputs set to low with their internal pull-up disabled. to configure a gpio pin as output and drive it low, select the gpio function in the iocon register, select output in the gpio dir register, and write a 0 to the gpio port register for that pin. di sable the pull-up in the pin?s iocon register. in addition, it is recommended to configure all gpio pins that are not bonded out on smaller packages as outputs driven low with their internal pull-up disabled. [1] i = input, o = output, ia = inactive (no pull- up/pull-down enabled), f = floating, pu = pull-up. 14.5 pin states in di fferent power modes [1] default and programmed pin states are retained in sleep, deep-sleep, and power-down modes. table 29. termination of unused pins pin default state [1] recommended termination of unused pins reset /pio0_5 i; pu in an applicati on that does not use the reset pin or its gpio function, the termination of this pin depends on w hether deep power-down mode is used: ? deep power-down used: connect an external pull-up resistor and keep pin in default state (input, pull-up enabled) during all other power modes. ? deep power-down not used and no external pull-up connected: can be left unconnected if internal pull-up is disabled and pin is driven low and configured as output by software. all pion_m (not open-drain) i; pu can be left unconnected if driven low and configured as gp io output with pull-up disabled by software. pion_m (i2c open-drain) ia can be left unconnected if driven low and configured as gpio output by software. vrefp - tie to vdd. vrefn - tie to vss. table 30. pin states in different power modes pin active sleep deep-sleep/power- down deep power-down pion_m pins (not i2c) as configured in the iocon [1] . default: internal pull-up enabled. floating. pio0_4, pio0_5 (open-drain i2c-bus pins) as configured in the iocon [1] . floating. reset reset function enabled. default: input, internal pull-up enabled. reset function disabled; floating; if the part is in deep power-down mode, the reset pin needs an external pull-up to reduce power consumption. pio0_16/ wakeup as configured in the iocon [1] . wakeup function inactive. wake-up function enabled; can be disabled by software. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 72 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 15. package outline fig 43. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 11 0 20 11 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 73 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller fig 44. package outline (hvqfn33 5x5) references outline version european projection issue date iec jedec jeita mo-220 hvqfn33f_po 11-10-11 11-10-17 unit (1) mm max nom min 0.85 0.05 0.00 0.2 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 0.5 3.5 a 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm bc 0.30 0.18 d (1) a (1) d h e (1) e h ee 1 e 2 l 3.5 vw 0.1 0.1 y 0.05 0.5 0.3 y 1 0.05 0 2.5 5 mm scale 1/2 e ac b v c w terminal 1 index area a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area 1/2 e lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 74 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 16. soldering fig 45. reflow soldering of the tssop20 package dimensions in mm ay by d1 d2 gy hy p1 c gx sot360-1_fr hx sot360-1 solder land occupied area footprint information for reflow soldering of tssop20 package ay by gy c hy hx gx p1 generic footprint pattern refer to the package outline drawing for actual layout p2 (0.125) (0.125) d1 d2 (4x) p2 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.450 7.300 0.650 0.750 lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 75 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller fig 46. reflow soldering of the hvqfn33 package (5x5) footprint information for reflow soldering of hvqfn33 package occupied area solder paste solder land dimensions in mm p 0.5 002aag766 issue date 11-11-15 11-11-20 ax ay bx c d 5.95 5.95 4.25 0.85 by 4.25 0.27 gx 5.25 gy 5.25 hy 6.2 hx 6.2 slx sly nspx nspy 3.75 3.75 3 3 0.30 0.60 detail x c sly d slx bx ay p nspy nspx see detail x gx hx gy hy by ax lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 76 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 17. abbreviations 18. references [1] lpc82x user manual um10800: http://www.nxp.com/documen ts/user_manual/um10800.pdf [2] lpc82x errata sheet: http://www.nxp.com/documents/errata_sheet/es_lpc82x.pdf [3] i2c-bus specification um10204 . [4] technical note adc design guidelines: http://www.nxp.com/documents /technical_note/tn00009.pdf table 31. abbreviations acronym description ahb advanced high-performance bus apb advanced peripheral bus bod brownout detection gpio general-purpose input/output pll phase-locked loop rc resistor-capacitor spi serial peripheral interface smbus system management bus tem transverse electromagnetic uart universal asynchronous receiver/transmitter lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 77 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 19. revision history table 32. revision history document id release date data sheet status change notice supersedes lpc82x v.1 20141001 product data sheet - - lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 78 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 79 of 81 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp semiconductors n.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com lpc82x all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights rese rved. product data sheet rev. 1 ? 1 october 2014 80 of 81 continued >> nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 functional description . . . . . . . . . . . . . . . . . . 12 8.1 arm cortex-m0+ core . . . . . . . . . . . . . . . . . . 12 8.2 on-chip flash program memo ry . . . . . . . . . . . 12 8.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 12 8.4 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.6 nested vectored interrupt controller (nvic) . 13 8.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 14 8.7 system tick timer . . . . . . . . . . . . . . . . . . . . . . 14 8.8 i/o configuration . . . . . . . . . . . . . . . . . . . . . . . 14 8.8.1 standard i/o pad configuration . . . . . . . . . . . . 14 8.9 switch matrix (swm) . . . . . . . . . . . . . . . . . . . 15 8.10 fast general-purpose parallel i/o (gpio) . . . 16 8.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.11 pin interrupt/pattern match engine . . . . . . . . . 16 8.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.2 dma trigger input mux (trigmux). . . . . . . . 17 8.13 usart0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.14 spi0/1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.15 i2c-bus interface (i2c0/1/2/3) . . . . . . . . . . . . 18 8.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.16 sctimer/pwm . . . . . . . . . . . . . . . . . . . . . . . . 19 8.16.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.16.2 sctimer/pwm input mux (input mux) . . . . 20 8.17 multi-rate timer (mrt) . . . . . . . . . . . . . . . . . 21 8.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.18 windowed watchdog timer (wwdt) . . . . . . 21 8.18.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.19 self-wake-up timer (wkt). . . . . . . . . . . . . . . 21 8.19.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.20 analog comparator (acmp) . . . . . . . . . . . . . . 22 8.20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.21 analog-to-digital converter (adc). . . . . . . . . 23 8.21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.22 clocking and power control . . . . . . . . . . . . . . 24 8.22.1 crystal and internal osci llators . . . . . . . . . . . . 24 8.22.1.1 internal rc oscillator (irc) . . . . . . . . . . . . . . 25 8.22.1.2 crystal oscillator (sysosc) . . . . . . . . . . . . . . 25 8.22.1.3 internal low-power oscillator and watchdog oscillator (wdosc) . . . . . . . . . . . . . . . . . . . . 25 8.22.2 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.22.3 system pll . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.22.4 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.22.5 wake-up process . . . . . . . . . . . . . . . . . . . . . . 26 8.22.6 power control . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.22.6.1 power profiles . . . . . . . . . . . . . . . . . . . . . . . . 26 8.22.6.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.22.6.3 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 27 8.22.6.4 power-down mode . . . . . . . . . . . . . . . . . . . . . 27 8.22.6.5 deep power-down mode . . . . . . . . . . . . . . . . 27 8.23 system control . . . . . . . . . . . . . . . . . . . . . . . . 28 8.23.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.23.2 brownout detection . . . . . . . . . . . . . . . . . . . . 28 8.23.3 code security (code read protection - crp) 29 8.23.4 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.23.5 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.24 emulation and debugging . . . . . . . . . . . . . . . 30 9 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31 10 thermal characteristics . . . . . . . . . . . . . . . . . 32 11 static characteristics . . . . . . . . . . . . . . . . . . . 33 11.1 general operating conditions . . . . . . . . . . . . . 33 11.2 supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.3 electrical pin characteristics. . . . . . . . . . . . . . 36 11.4 power consumption . . . . . . . . . . . . . . . . . . . . 39 11.5 coremark data . . . . . . . . . . . . . . . . . . . . . . . . 45 11.6 peripheral power consumption . . . . . . . . . . . 46 11.7 electrical pin characteristics. . . . . . . . . . . . . . 47 12 dynamic characteristics. . . . . . . . . . . . . . . . . 50 12.1 flash/eeprom memory . . . . . . . . . . . . . . . . 50 12.2 external clock for the oscillator in slave mode 50 12.3 internal oscillators . . . . . . . . . . . . . . . . . . . . . 51 12.3.1 i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3.2 wktclkin pin (wake-up clock input) . . . . . . 53 12.3.3 sctimer/pwm output timing . . . . . . . . . . . . . 53 12.3.4 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3.5 spi interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 56 12.3.6 usart interface . . . . . . . . . . . . . . . . . . . . . . 59 13 characteristics of analog peripherals. . . . . . 60 nxp semiconductors lpc82x 32-bit arm cortex-m0+ microcontroller ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 1 october 2014 document identifier: lpc82x please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 13.1 bod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.2 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.3 comparator and internal voltage reference . . 64 14 application information. . . . . . . . . . . . . . . . . . 67 14.1 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14.2 xtal printed-circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.3 connecting power, clocks, and debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.4 termination of unused pins. . . . . . . . . . . . . . . 70 14.5 pin states in different power modes . . . . . . . . 71 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 72 16 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 76 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . 77 20 legal information. . . . . . . . . . . . . . . . . . . . . . . 78 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 78 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 20.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 79 21 contact information. . . . . . . . . . . . . . . . . . . . . 79 22 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 |
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